Traditionally, in the field of integrated circuit design, the length of time that a signal takes to go from a predetermined origin to a predetermined destination (herein, generally referred to as “timing”) is an important parameter. Integrated circuit designers typically include contributions from (1) transistors and/or other circuit devices (such as capacitors, resistors, diodes, etc.) and (2) wires when predicting or evaluating the timing of a particular design. As lines widths and device dimensions decrease, the relative contributions of wires to timing increase. At or below minimum or critical dimensions of 0.18 microns, wires become the major or dominant contributor to delays in timing.
Integrated circuits also generally have timing, or “clock,” circuitry thereon. Such timing circuitry generally ensures that signals are captured at predetermined locations on the chip at certain times. The times at which certain circuit components capture data in the signals is generally defined by the clock signal waveform and the distribution of the clock signal to component locations on the chip.
Place and route software is generally used by integrated circuit designers to place circuit structures and/or configure wiring in a design automatically or semi-automatically. One typical challenge for place and route software has been to place circuit components (e.g., transistors, capacitors, diodes, logic gates, flip-flops, latches, registers, etc.) in a manner leaving sufficient room for wires to interconnect them. A number of such software tools are available in the marketplace today. However, such commercially available tools generally do not distinguish between clocked circuit components, such as flip-flops, latches and registers, and combinational circuit elements that do not receive a clock signal, such as switches and logic gates. Consequently, such tools generally do not ensure, or “guarantee by design,” timing of signal paths from any clocked circuit component to the next downstream clocked circuit component. Rather, timing in a design is generally met by iteratively designing circuitry, then analyzing or determining the timing of various signal paths through the circuitry, and changing the design to shorten the signal paths that violate certain predetermined timing constraints or parameters.
For example, in at least one conventional clock tree synthesis (CTS) tool, buffers placed in locations in a clock tree layout specified by the tool force the relocation of other circuit structures that may have already been placed in those locations. That first relocation exercise is likely to result in further relocations of structures residing in locations where the relocated structures are placed, and so on, until all existing structures are relocated in allowable, unoccupied locations. In a design that includes about 100K flip-flops, the conventional CTS tool places about 20K clock buffers in the layout. It is not unusual for the placement of those 20K buffers to affect the locations of about 200K cells in the layout.
The ever-increasing demands on integrated circuit designers and manufacturers to create chips of increasing density, decreasing wire and transistor widths, and decreasing power supply and power consumption make it increasingly difficult, if not impossible, to ensure meeting timing constraints automatically or “by design.” Increasing the complexity, flexibility and/or functionality of the circuitry on a chip exacerbates these challenges. Thus, what is needed is a tool with which integrated circuit designers can ensure timing of signals from any given origin to any given destination in a circuit.